1. Field of the Invention
The present invention relates to a semiconductor device comprising an active layer and an electron supply layer and utilizing a two-dimensional electron gas produced in an interface between the layers.
2. Description of the Related Art
AlGaN/GaN HJFETs are considered as promising devices with high power and high withstand voltage. A conventional AlGaN/GaN HJFET has a configuration in which a plurality of gallium nitride group semiconductor layers are stacked on a substrate, for example as disclosed in U.S. Pat. No. 5,192,987 by M. A. Khan. Each semiconductor layer has uniform composition in a horizontal plane perpendicular to the thickness direction of the layers.
In semiconductor devices of this kind, one of important considerations is to simultaneously realize high withstand voltage between a gate and a drain and a higher current density in an active layer, and an electrode of low contact resistance. To this end, it is necessary to vary distribution of carriers in a channel layer and a surface layer within a plane to increase withstand voltage between a gate and drain by reducing a channel concentration in an area under the gate or between the gate and drain and to realize low contact resistance by increasing a channel concentration in source and drain areas. For this purpose, conventionally, an area in a low carrier concentration and an area in a high carrier concentration are separately formed by performing ion implantation to partially change a dose, or areas in different carrier concentrations are separately formed by stacking layers in different carrier concentrations and then recess-etching a portion of the layers. For example, in AlGaAs/GaAs, GaAs doped in high concentration is formed on a surface to form an ohmic electrode, and the heavily doped area is partially removed to form a gate electrode.
In AlGaN/GaN, however, when a heterojunction is formed on a (0001) surface, more carriers are induced with a piezo effect and a spontaneous polarization effect than with a doping concentration. Even when layers in different doping concentrations are formed and a portion thereof is removed, the effect of providing a difference in electron concentration within a plane is not produced sufficiently. The piezo effect is determined by the composition of stacked layers, and induced carriers depend on the thickness of the layer if it is smaller than a critical thickness at which dislocation occurs. Thus, while an effect can be obtained to some extent by partially removing a uniform film through recess-etching, the effect is insufficient to form a greater difference in carrier concentration. In addition, a large difference in thickness is required to obtain a large difference in concentration, which makes it difficult to achieve a reduced difference in height.
On the other hand, it is known that gallium nitride semiconductor materials typically have a low activation rate from ion implantation, and thus contact resistance tends to be high. To address such a problem, J. Burm et al. have reported a configuration in which AlGaN having uniform composition in an AlGaN/GaN HJFET is recess-etched in Solid-State Electronics Vol.41, No.2, pp247, 1997. This configuration provides a small reduction in contact resistance and achieves a tolerable effect, although it is difficult to obtain a currently desired level of low contact resistance. While a configuration including a heavily doped GaAs cap layer formed on a surface of AlGaAs is employed in the GaAs group, this results in an increase in contact resistance conversely due to piezo charge in the AlGaN/GaN group.
The present invention has been made in view of the aforementioned circumstances, and it is an object of the present invention to produce a distribution of two-dimensional electrons serving as carriers in a horizontal plane perpendicular to a thickness direction of layers to form a desired device configuration. Specifically, when the present invention is applied to a transistor configuration, the present invention intends to improve withstand voltage between a gate and a drain by reducing a channel concentration under the gate and to realize low contact resistance by increasing a channel concentration in source and drain areas. When the present invention is applied to a monolithic microwave integrated circuit, the present invention intends to form a higher resistance element and a lower resistance element separately with simple steps and good controllability.
According to the present invention, provided is a semiconductor device comprising an active layer, and an electron supply layer in which induced charge including piezo charge is produced, the active layer and the electron supply layer being stacked in this order and having an interface between them at which a two-dimensional electron gas is formed, wherein the induced charge has a distribution within a horizontal plane perpendicular to the thickness direction of the layers and a distribution of two-dimensional electron concentrations is formed within the horizontal plane in accordance with the distribution of the induced charge.
With the semiconductor device, since the distribution of two-dimensional electron concentrations is formed in accordance with the distribution of the induced charge including piezo charge within the horizontal plane, it is possible to form an area of high channel resistance and an area of low channel resistance with good controllability. The induced charge includes both charge due to piezo polarization and charge due to spontaneous polarization. To produce such induced charge significantly, both active layer and electron supply layer are preferably formed of a group III nitride semiconductor. A crystal growth surface in this case is preferably a (0001) surface. It should be noted that, in this specification, the (0001) surface in group III nitride semiconductor crystal refers to a hatched surface in an arrangement shown in FIG. 3.
The semiconductor device may be configured such that a first area having a relatively low two-dimensional electron concentration is formed under a gate electrode and a second area having a relatively high two-dimensional electron concentration is formed under a source electrode, under a drain electrode, between the gate electrode and the drain electrode, or between the gate electrode and the source electrode. When such a configuration is used, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, while a channel concentration in source and drain areas is increased to realize low contact resistance. The first area may be formed in at least a portion of a region under the gate electrode, and the second area may be formed in at least a portion of the aforementioned regions. For example, the second area may be formed only in a portion of a region under the source electrode. It is preferable, however, that the second area is provided for each of the source and drain sides to allow a reduction in both source electrode resistance and drain electrode resistance. As an example of preferred arrangements of the first and second areas, the first area is formed under the gate electrode and in an area closer to the gate electrode between the gate and drain, and the second area is formed in an area where the first area is not formed between the source and drain and under each of the source and drain electrodes.
The semiconductor device may be configured such that the area having a relatively low two-dimensional electron concentration is used as a higher resistance element, and the area having a relatively high two-dimensional electron concentration is used as a lower resistance element. When such a configuration is used, the higher resistance element and lower resistance element can be formed separately with simple steps and good controllability. In the present invention, xe2x80x9ca relatively low two-dimensional electron concentrationxe2x80x9d refers to a two-dimensional electron concentration lower than a two-dimensional electron concentration in the area used as the lower resistance element, while xe2x80x9ca relatively high two-dimensional electron concentrationxe2x80x9d refers to a two-dimensional electron concentration higher than the two-dimensional electron concentration in the area used as the higher resistance element.
According to the present invention, provided is a semiconductor device comprising an active layer, and an electron supply layer formed in contact with an upper portion of the active layer and having tensile strain, wherein the active layer is made of InxGa1xe2x88x92xN (1xe2x89xa7Xxe2x89xa70) and the electron supply layer is formed of a plurality of AlGaN layers having different average Al contents in contact with the upper portion of the active layer.
With the semiconductor device, the plurality of AlGaN layers having different average Al contents can preferably produce a distribution of induced charge including piezo charge within a horizontal plane, and a distribution of two-dimensional electron concentration is formed in accordance with the distribution. It is thus possible to form an area of high channel concentration and an area of low channel concentration with good controllability.
The semiconductor device may be configured such that an Al content of one or two or more layers of the plurality of AlGaN layers increases with distance from the active layer. This configuration enables a more significant distribution of induced charge within the horizontal plane to produce a significant distribution of two-dimensional electron concentrations.
The semiconductor device may be configured to further comprise a gate electrode, and a source electrode and a drain electrode formed on both sides of the gate electrode, wherein the gate electrode is formed in contact with one of the plurality of AlGaN layers, and the other layers having a higher Al content than the one layer are disposed between the gate electrode and the drain electrode and between the gate electrode and the source electrode. With such a configuration, a channel concentration under a gate can be reduced to improve withstand voltage between the gate and a drain, while a channel concentration in source and drain areas can be increased to realize low contact resistance.
The semiconductor device may be configured such that an area where a layer of the plurality of AlGaN layers having a relatively low Al content is formed is used as a higher resistance element and an area where a layer of the plurality of AlGaN layers having a relatively high AL content is formed is used as a lower resistance element. In this manner, the higher resistance element and lower resistance element can be separately formed with simple steps and good controllability. In the present invention, xe2x80x9ca relatively low Al contentxe2x80x9d refers to an Al content lower than the Al content in the area used as the lower resistance element, while xe2x80x9ca relatively high Al contentxe2x80x9d refers to an Al content higher than the Al content in the area used as the higher resistance element.
According to the present invention, provided is a semiconductor device comprising an active layer, an electron supply layer formed in contact with an upper portion of the active layer and having tensile strain, and a strain layer formed in contact with a part of an upper portion of the electron supply layer and having tensile strain, the active layer being made of InxGa1xe2x88x92xN (1xe2x89xa7Xxe2x89xa70), the electron supply layer being made of AlyGa1xe2x88x92xN yN (Yxe2x89xa70), and the strain layer being made of AlzGa1xe2x88x92zN (1xe2x89xa7Z greater than Y).
In the semiconductor device, the strain layer has a higher Al content and a greater tensile strain than the electron supply layer. In an area where the strain layer is formed, large induced charge is produced due to piezo polarization and spontaneous polarization, and in accordance with this, a two-dimensional electron concentration is remarkably increased. Thus, an area of high channel resistance and an area of low channel resistance can be formed with good controllability, and additionally, a large difference in resistance can be obtained.
The semiconductor device may be configured such that an Al content in the electron supply layer or strain layer increase with distance from the active layer. This can produce a more significant distribution of induced charge within a horizontal plane to result in a significant distribution of two-dimensional electron concentrations.
The semiconductor device may be configured to comprise a gate electrode, and a source electrode and a drain electrode formed on both sides of the gate electrode, wherein the gate electrode is formed in contact with the electron supply layer and the strain layer is disposed between the gate electrode and the drain electrode and between the gate electrode and the source electrode. With such a configuration, a channel concentration under a gate or in an area between the gate and a drain can be reduced to improve withstand voltage between the gate and drain, while a channel concentration in source and drain areas can be increased to improve low contact resistance. If the strain layer is formed in contact with the source electrode and drain electrode when the configuration is employed, a low resistance area under the strain layer is close to the source electrode and drain electrode to allow a further reduction in contact resistance. When the gate electrode is formed to extend on the strain layer, concentration of electric fields can be alleviated between the gate and drain and a voltage withstanding characteristic can be improved.
The semiconductor device may be configured such that an area where the strain layer is disposed is used as a lower resistance element and an area where the strain layer is not disposed is used as a higher resistance element. In this manner, the higher resistance element and lower resistance element can be separately formed with simple steps and good controllability.
According to the present invention, provided is a semiconductor device comprising an active layer, and an electron supply layer formed in contact with an upper portion of the active layer and having tensile strain, wherein an Al content in the electron supply layer increases with distance from the active layer, a first area having a relatively low Al content is formed at an upper surface of the electron supply layer, and a second area having a relatively high Al content is formed at an upper surface of the electron supply layer.
An example of such a semiconductor device is one obtained by forming a layer having a uniformly increasing Al content and then etching a portion thereof to form a recess (see FIG. 13 and the like). In the present invention, xe2x80x9ca relatively low Al contentxe2x80x9d refers to an Al content lower than the Al content in the area used as the lower resistance element, while xe2x80x9ca relatively high Al contentxe2x80x9d refers to an Al content higher than the Al content in the area used as the higher resistance element. In the semiconductor device, the second area has a greater tensile strain than the first area. For this reason, in the second area, large induced charge is produced due to piezo polarization and spontaneous polarization, and in accordance with this, a two-dimensional electron concentration is remarkably increased. It is thus possible to form an area of high channel resistance and an area of low channel resistance with good controllability, and moreover, a large difference in resistance can be obtained.
The semiconductor device may be configured to comprise a gate electrode, and a source electrode and a drain electrode formed on both sides of the gate electrode, wherein the gate electrode is formed in contact with the first area and the second area is formed under the source electrode, under the drain electrode, between the gate electrode and the drain electrode, or between the gate electrode and the source electrode. With such a configuration, a channel concentration under a gate can be reduced to improve withstand voltage between the gate and a drain, while a channel concentration in source and drain areas can be increased to realize low contact resistance. The first may be formed in at least a portion of a region under the gate electrode, and the second area may be formed in at least a portion of the aforementioned regions. For example, the second area may be formed only in a portion of a region under the source electrode. It is preferable, however, that the second area is provided for each of the source and drain sides to allow a reduction in both source electrode resistance and drain electrode resistance. As an example of preferred arrangements of the first and second areas, the first area is formed under the gate electrode and in an area closer to the gate electrode between the gate and drain, and the second area is formed in an area where the first area is not formed between the source and drain and under each of the source and drain electrodes.
The semiconductor device may be configured such that the first area is used as a higher resistance element and the second area is used as a lower resistance element. In this manner, the higher resistance element and lower resistance element can be separately formed with simple steps and good controllability.
When each of the aforementioned semiconductor devices is provided with the gate electrode and drain electrode, a second gate electrode may be provided between them. This can alleviate concentration of electric fields between the gate and drain and improve a voltage withstanding characteristic.
The effects of the present invention are hereinafter described in detail.
The present invention creates induced charge due to piezo polarization and spontaneous polarization in the electron supply layer and forms a distribution of two-dimensional electron concentrations within a horizontal plane in accordance with the degree of the induced charge. Specifically, an Al content above a channel can be varied in the horizontal plane to adjust a portion of the channel under a high Al content area to have a high electron concentration and a portion of the channel under a low Al content area to have a low electron concentration. In this manner, the present invention provides a configuration for controlling piezo charge and spontaneous polarization effects within the plane to more effectively change a channel electron concentration partially within the plane. The configuration is utilized as required under a gate electrode, in a drift area, under an ohmic electrode, under a second gate electrode or the like, thereby realizing a gate with high withstand voltage, a low resistance contact and the like.
For example, at least two ore more AlGaN layers having different composition are disposed on an InxGa1xe2x88x92xN (1xe2x89xa7Xxe2x89xa70) oriented on a (0001) surface to change a piezo effect and a spontaneous polarization effect within a plane, thereby making it possible to obtain a distribution of electron concentrations in the InGax (1xe2x89xa7Xxe2x89xa70) layer within the plane. Such a configuration is realized by forming an AlGaN layer of an electron supply layer from two ore more layers having different Al contents and removing a portion of one of the layers through etching or forming it through selective growth.
Japanese Patent Laid-open Publication No. 11-261051 and Japanese Patent Laid-open Publication No. 11-274474 have made disclosure as to the possibility of increasing a two-dimensional electron concentration by changing composition of AlGaN serving as an electron supply layer in a thickness direction. Techniques disclosed in the publications, however, intend to improve electron mobility in a two-dimensional gas by changing the Al content in the thickness direction or to narrow an area in which a two-dimensional electron gas is formed. The publications do not disclose a configuration in which an Al content is varied within a horizontal plane perpendicular to a thickness direction, and an Al content within a horizontal plane is uniform in the disclosures. Particularly, it is the study by the present inventors that first revealed that an Al content above a channel can be varied within a horizontal, plane to adjust a portion of the channel under a high Al content area to have a high electron concentration and a portion of the channel under a low Al content area to have a low electron concentration.
The effects of the present invention are hereinafter described with reference to the drawings.
FIG. 6 is a cross section of a semiconductor device of the present invention in which at least two or more AlGaN layers 4, 5 with different composition formed on an InxGa1xe2x88x92xN (1xe2x89xa7Xxe2x89xa70) layer vary a piezo effect within a plane to provide a distribution of electron concentrations in the InxGa1xe2x88x92xN (1xe2x89xa7Xxe2x89xa70) layer within a plane. FIG. 8 is a schematic diagram showing a conduction band in area (a) near a channel from a surface below a source and a drain toward a substrate. FIG. 9 is a schematic diagram showing a conduction band in area (b) near a channel from a surface under a gate toward the substrate. An average Al content of the AlGaN layer present above the channel in area (a) is higher than an average Al content of the AlGaN layer present above the channel in area (b). As a result, in area (a), a greater piezo effect and a greater spontaneous polarization effect can be obtained to achieve carriers of a high electron density in the InxGa1xe2x88x92xN (1xe2x89xa7Xxe2x89xa70) layer.
FIG. 7 shows a configuration of another example of a semiconductor device according to the present invention in which an AlGaN layer serving as an electron supply layer is formed of two ore more layers (Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5) with different Al contents and one of the layers is removed partially through etching or formed through selective growth to vary a piezo effect within a plane, thereby obtaining a distribution of electron concentrations in InxGa1xe2x88x92xN (1xe2x89xa7Xxe2x89xa70) layer 6 within a plane. Al0.1Ga0.9N layer 5 is formed on GaN layer 6, and Al0.3Ga0.7N layer 4 is formed on a portion of Al0.1Ga0.9N layer 5. FIGS. 10 and 11 are schematic diagrams showing conduction bands near channels from a surface toward a substrate in area (c) including Al0.3Ga0.7N layer 4 and area (d) including no Al0.3Ga0.7N layer 4, respectively. In area (d) including no Al0.3Ga0.7N layer 4, electrons are induced by a piezo effect and a spontaneous polarization effect induced by Al0.1Ga0.9N layer 5 and in accordance a doping amount. On the other hand, in area (c) including Al0.3Ga0.7N layer 4, a greater piezo effect and a greater spontaneous polarization effect can be obtained due to a high Al content in addition to a doped donor amount, and thus it is possible to provide carriers of a high electron density in GaN layer 6.
In an AlGaN/GaN HJFET configuration, a higher channel electron concentration is typically induced by a piezo effect than by doping. For this reason, in contrast with a conventional uniform AlGaN layer as shown in FIG. 1, the configuration including partially different AlGaN contents within a plane is employed as shown in FIG. 6, or a strain layer with a high Al content is provided to cause a great piezo effect which results in a large difference from a portion including no strain layer as shown in FIG. 7. According to the present invention, a large difference in channel electron concentration can be obtained in a horizontal direction along the surface of the device to simultaneously form a high resistance area and a low resistance area in a conduction layer with a small difference in height, resulting in a desired channel electron concentration depending on areas. When an area in a low channel electron concentration is used under a gate electrode or in a drift area between a gate and drain, high gate withstand voltage can be realized. On the other hand, a layer in a high channel electron concentration can be formed under an ohmic electrode, or a high channel electron concentration can be extended to a portion near an ohmic electrode. With the configuration, resistors with largely different values can be formed on the same substrate by using a channel layer.
As described above, according to the present invention, since an area in a high electron concentration and an area in a low electron concentration can be separately formed within a plane with a wide difference in concentration, the low electron concentration can be provided for a region requiring high withstand voltage and the high electron concentration can be provided for a region requiring low contact resistance. Thus, the design of a device configuration is facilitated since it is possible to separately form an area which positively utilizes a piezo effect and a spontaneous polarization effect and an area which does not make much use of such effects, and moreover, device characteristics are dramatically improved. The ability to form a conduction layer with largely different resistance values within the same plane is advantages in terms of circuit configuration. The small difference in height also facilitates the process.
As described above, according to the present invention, a distribution of two-dimensional electron concentrations is formed in accordance with a distribution of induced charge including piezo charge within a horizontal plane. It is thus possible to form an area of high channel resistance and an area of low channel resistance with a small difference in height. When the present invention is applied to a transistor configuration, withstand voltage between a gate and a drain is improved by reducing a channel concentration under the gate, while low contact resistance can be realized by increasing a channel concentration in source and drain areas. When the present invention is applied to a monolithic microwave integrated circuit, a higher resistance element and a lower resistance element can be separately formed with simple steps and good controllability. The ability to simultaneously form a conduction layer with largely different channel resistance within the same plane is also advantageous in terms of circuit configuration.